CORPORATE TRAINING

CORPRATE TRAINING

  • Customized corporate training programs offered towards enabling fast and productive integration of fresh hires. The training sessions and labs shall be delivered either from Logosent training facilities or from with in the client company environment.
  • The contents are tailored to enable direct ramp of fresh hires on VLSI design/verification projects beyond the training period spanning 3-4 months.
  • During the course of the training, the students will be required to conduct routine project planning/tracking, team meetings, weekly reports, reviews and multiple presentations, in line with the standard Industry practices.

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Titbits for thought

Transistors – a few atoms wide, often numbering in 100s of millions. All intricately connected by a multilayer network of metal routes. Designed to the specifications driven by complex customer applications. The fruit of tireless work and passion 3b4ffd06-8821-4802-932e-ce281a6ae662-large

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INDIVIDUAL TRAINING

DIGITAL DESIGN AND VERIFICATION TRAINING

Verilog Primer Labs

CONTENTS

A refresher course covering all commonly used constructs in Verilog including:

  • File operations, VCD and IO functions
  • Behavioural Vs Structural coding
  • Parameterized and Generated (using Perl) code
  • Drive levels in Verilog
  • Behavioural constructs like case, if and conditional assignments
  • Verilog operators
  • Forever, while, repeat, for loops
  • User Define Primitives (UDP)
  • Tasks and functions
  • Compiler directives

The student will go through examples of each construct to build thoroughness through simulations and sand-box experiments.


Digital Design Essentials

THEORY

  • Buses, Bus Protocols and Bus Interfaces
  • Clocks: Overview, timing, clock-gating, clock-tree
  • Synchronization
  • Resets
  • Typical side-band signals in IPs and SOCs
  • Finite State Machines: Moore and Mealy
  • Power management techniques and related components
  • Design For Test and Manufacturability: Overview and operation sequences
  • Logic synthesis, Scan insertion and Formal verification: Overview
  • Physical design flows: Overview
  • IP Blocks: Overview with example
  • IP development phases
  • SOC: Overview with example
  • SOC development phases
  • System block diagram
  • Power Performance Area (PPA) trade-offs
  • Special considerations for implementing clock structures
  • RTL coding: Key considerations

LABS

  • LINUX Environment: LINUX commands, VI editor expert level usage, aliases/shell scripts
  • Verilog coding and simulation of shift-registers, value detect, counters, multi-clock domains with synchronization
  • Synthesis and gate-netlist analysis using schematic viewers

Specification and Microarchitecture
  • Functional requirements definition
  • DFTM requirements definition
  • Power Performance and Area budgets
  • High Level Block Diagram and feature list
  • Compliance standards
  • External pins and IO functionality
  • Register and Memory map
  • Clocking and reset requirements
  • Interface timing requirements
  • Power management
  • Electrical requirements

MICRO-ARCHITECTURE DEVELOPMENT

  • Design partitioning and submodule definitions
  • Internal clocking and reset architecture
  • Inter-submodule interface descriptions and timings
  • Submodule level block-diagrams for major functionality
  • Flow diagrams for all Finite State Machines
  • Register and memory selection to meet PPA requirements
  • RTL hierarchy definitions and module pin-naming
  • DFTM implementation specifics
  • Reset/Idle state definitions for all registers and interface pins

Introduction to Verification

THEORY

  • Verification: Evolution, challenges and the problem space
  • Concepts of timing and synchronization in the verification world
  • Testbench infrastructure
  • Testbench components
  • System Verilog: Capabilities and key constructs
  • Negative tests, Performance estimation, Dynamic binding
  • Repository: SVN, CVS RCS
  • Basic scripting for automation
  • Coverage driven Verification Plan

LABS

  • Build your first System Verilog Test Bench
  • Exercise IPC
  • Test and report some sample codes


Verification using Classes - An Object Oriented Approach

THEORY

  • Object Oriented Programing (OOP): Overview
  • OOP: Detailed study, commonly used OOP constructs
  • Examples of Class definition, components, handles etc.
  • Layered testbenches with generator/driver transactions
  • A practical instance of injecting error scenario

LABS

  • Create Class to test as counter design
  • Extend the Class to test a different counter design
  • Instantiate base and extended Classes
  • Integrate events in class/objects

Verification using assertions

THEORY

  • Introduction to Assertions
  • Types of Assertions
  • Actions Message and Severity
  • Concurrent => Properties
  • Sequences and ## Delay
  • Assertion as a Verification Strategy
  • Repeated regular expressions
  • Sample value functions
  • Conditioning and sequences using Implication operators

LABS

  • Examples of various constructs discussed
  • Immediate/concurrent contrast
  • Sequencing overlap AND/OR operator


Verification - C-DPI, SystemC and Introduction to UVM

THEORY

  • Argument passing and results
  • Calling ‘C’ from System Verilog
  • Calling System Verilog from ‘C’
  • System C
  • Universal Verification Methodology (UVM) Introduction
  • UVM: Factory Infrastructure

LABS

  • Write C-DPI from system Verilog to compute sine/cosines of a continuous vector
  • Pass the argument in C DPI such that there is minimum context switch between simulations
  • Contrast the outcome of the two approaches listed above
  • Setup a UVM testbench infrastructure


  • IP Development Project
    • IP requirements provided by the instructor
    • Planning and execution of the full IP development cycle to meet the requirements

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    Interview and career preparation classes
    • Presentation skills
    • Planning and tracking
    • Key behavioural aspects to be internalized
    • DOs and DONTs in the corporate world
    • Resume Development support
    • Mock interviews
    • Placement support through references for qualifying students

    Placement support (if requested) provided for all qualifying trainees.

    Titbits for thought

    Attitude matters! 8658b04a-38c7-4aa4-9404-17dab2a72039-large

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    LEARN@

    An affordable launch pad for students and young professionals seeking a fast entry and career growth in the Semiconductor engineering arena.

    Industry readiness built through systematic projects and behavioural training, all delivered by 20+ years experienced professionals from top Multi-National Companies.

    All training labs implemented around industry standard tools and environments:

    • LINUX
    • Perl
    • ModelSim
    • Xilinx Vivado FPGA compiler

    Titbits for thought

    Power management is the buzz-word these days! be4f60ce-f430-4f4b-a01c-3c55c6b2bb4e-large

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